Layout design of metal-insulator-metal capacitor array for reducing parasitic influences

摘要

In this paper, a layout design of an accurate Metal-insulator-Metal (MIM) capacitor array for reducing parasitic influences is presented. Parasitic capacitance due to interconnecting wires is well-matched. Parasitic resistance can be reduced for less routing track used. Post layout simulation results show that percentage errors of capacitor ratios are generally 0.02% A 16-bit analog-to-digital converter (ADC) including MIM capacitor arrays shows 81dB of SFDR without capacitor mismatch calibration.