Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing

摘要

Capacitor sizing is a crucial step when designing charge-scaling digital-to-analog converters (DACs). Larger capacitor size can achieve better circuit accuracy and performance due to less impact from process gradient, parasitic mismatch, and local variation. However, it also results in larger chip area and higher power consumption. The size of binary-weighted capacitors in charge-scaling DACs is highly sensitive to the routing parasitics. Unmatched routing parasitics among binary-weighted capacitors will lead to large capacitor size for satisfying circuit accuracy and performance. Previous work focuses on the study of generating high-quality common-centroid placement of unit capacitor arrays while ignoring routing parasitics. None of them address the sizing of binary-weighed capacitors. This paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state-of-the-art approaches.