A low-jitter digital-to-time converter with look-ahead multi-phase DDS

摘要

We propose a multi-phase Direct Digital Synthesizer (DDS) based Digital to Time Converter (DTC), for application in fractional-N Digital Phase Locked Loops (DPLLs). The proposed DTC employs (i) multiple DDSs operating with incremental delay for reduced quantization step size, and (ii) a phase-advanced ROM in these DDSs for correct waveform extrapolation. The incrementally delayed output from multiple DDSs allows reduction in harmonics associated with the quantized steps, and the look-ahead feature of phase advanced ROM allows DTC operation even at the Nyquist rate. The DTC, designed in 65 nm CMOS-LL technology, achieves 1.2 ps jitter with 10 mW power consumption, while operating at 4.8 GHz input frequency. Also, the fractional-N DPLL employing the proposed multi-phase DDS based DTC in its feedback path is able to attain ???341 dB as Figure of Merit, which is the best amongst the published results, with a very low settling time-jitter product.