Recent studies have shown that Phase Change Memory faces significant write disturbance (WD) when scaling in deep submicron regime, i.e., resetting a cell may disturb the values of its adjacent cells if these cells are in amorphous state. A preventive approach to mitigate WD errors is to allocate sufficient inter-cell thermal band. However, this approach greatly reduces chip capacity due to low cell density. A cost effective approach VnC (verify-and-correct), relies on Verification after each write and Correction if errors do happen. Simple VnC improves chip capacity but introduces large performance degradation. In this paper, we propose to exploit the cell level write imbalance to mitigate WD errors. A memory line is often split into cell groups so that the cells within one group are written synchronously. We observe that only few cell groups are critical, which prolong write latency and degrade system performance. By rescuing the disturbance errors from critical groups with unused Error Correction Pointer(ECP) entries, we can greatly minimize the VnC impact on performance. The experimental results show that our proposed scheme effectively eliminates VnC overhead with minimal hardware adjustments.
展开▼
