Phase Change Memory (PCM) has better scalability and smaller cell size comparing to DRAM. However, further scaling PCM cell in deep sub-micron regime results in significant thermal based write disturbance. Naively allocating large inter-cell space increases cell size from ideal 4F^2 to 12F^2. While a recent work mitigates write disturbance along word-lines through disturbance resilient data encoding, which can shrink PCM cell size from 12F^2 to 8F^2, it is ineffective for write disturbance along bit-lines, which is more severe due to widely adopted uTrench structure in constructing PCM cell arrays.ududIn this thesis, we propose SD-PCM, an architecture to achieve reliable write operations in Super Dense PCM. In particular, we focus on mitigating write disturbance along bit-lines such that we can construct super dense PCM chips with 4F^2 cell size, i.e., the minimal for diode-switch based PCM. Based on simple verification-n-correction (VnC), we propose LazyCorrection and PreRead to effectively reduce VnC overhead and minimize cascading verification during write. We further propose (n:m)-Alloc for achieving good tradeoff between VnC overhead minimization and memory capacity loss. Our experimental results show that, comparing to a write disturbance-free low density PCM, SD-PCM achieves 80% capacity improvement in cell arrays while incurring around 0-10% performance degradation when using different (n:m) allocators.
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