Automated latchup analysis

摘要

A new simulation approach to the analysis of the low voltage latchup in CMOS process and the high voltage latchup in BCD process technologies is presented. The approach uses new automated numerical algorithm simulating real standard three-stage latchup test and relies on parameterized 2-D mixed-mode simulation of a finite-element model (FEM) structure that represents the parasitic structure formed in the physical IC layout.