A 128-kb 10 power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology

摘要

A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.