A 2-transistor sub-1V low power temperature compensated CMOS voltage reference

摘要

This paper presents the design of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. Besides that, the two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a 0.18?m standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from −20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA. The complete circuit including the current source and the 2-transistor Self-Cascode MOSFET occupies an area of 0.01mm.