A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

摘要

A 100MS/s 10-bit ADC design using a 130nm standard CMOS technology is presented in this paper. The proposed design adopted the split capacitor array digital-to-analog converter (DAC) to build successive approximation register (SAR) analog-to-digital converter (ADC) structure using a single input. On-chip mismatch calibration feature is utilized to compensate the capacitor mismatches of the DAC and to calibrate the input offset voltage of a comparator. The proposed calibration uses a simple and efficient algorithm and optimizes the capacitor mismatches of the DAC by using inverter-based capacitor comparison technique and by controlling additional auxiliary capacitor arrays in calibration mode. The ADC achieves 41.9dB of SNR and consumes 1.1mW with 1.2V supply voltage.