Integration of a multi-layer Inter-Gate Dielectric with hybrid floating gate towards 10nm planar NAND flash

摘要

We demonstrate the integration of multi-layer Inter-Gate Dielectrics (IGD) together with a thin Hybrid Floating Gate (HFG), in aggressively scaled planar NAND cells. The results show that excellent memory performance is obtained in short gate length transistors, with good retention and endurance. Simulations indicate that such gate stacks can drive the planar NAND Flash scaling down to 10 nm node.