In this paper, we propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. In subthreshold digital circuits, though the circuits can achieve ultra-low power dissipation, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. In particular, because the write operation of SRAM is prone to fail due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a less write operation failure rate and smaller write time variation than a conventional 6T SRAM.
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机译：在本文中，我们提出了一种具有改进的写入能力的亚阈值静态随机存取存储器（SRAM）电路架构。在亚阈值数字电路中，虽然电路可以实现超低功耗，但由于制造工艺和温度，性能显着降低了阈值电压变化。特别地，由于SRAM的写入操作由于NMOSFET和PMOSFET之间的阈值电压的不平衡而易于失效，所以不能确保稳定的操作。为了实现SRAM的稳健写入操作，我们通过使用使用片上阈值电压监测电路的自适应电压缩放技术开发了补偿技术。监控电路通过片上电路配置检测MOSFET的阈值电压。通过使用监控电压作为SRAM电池的电源电压，可以补偿写操作。 Monte Carlo模拟表明，所提出的SRAM架构表现出较少的写入操作失败率和比传统的6T SRAM更小的写入时间变化。
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