首页> 外文会议>ACM/EDAC/IEEE Design Automation Conference >Design, CAD and technology challenges for future processors: 3D perspectives
【24h】

Design, CAD and technology challenges for future processors: 3D perspectives

机译:未来处理器的设计,CAD和技术挑战:3D观点

获取原文

摘要

Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level innovation, which provided performance improvement in each processor generation. However, future processor designs face a number of key challenges in sustaining the growth trends. The dawn of the 22nm node, and beyond, marks an era of new trends and challenges; where the cost and complexity associated with each technology node is increasing at much faster rate than the device performance gains. Novel tools and design methodologies are needed to not only compensate for these challenges but also to leverage emerging technologies to achieve the desired performance in future processor architectures. Technology alternatives such as 3D integration have attracted significant interest as an additional way of sustaining the density scaling and performance growth.
机译:技术缩放为半导体行业提供了一种成功符合三十年来表现性能的方法。通过电路和建筑级创新的成功进一步推动了这种计算能力,从而提供了每个处理器生成的性能改进。然而,未来的处理器设计面临着维持增长趋势的一些关键挑战。 22nm节点的黎明,而超越,标志着新趋势和挑战的时代;在与每个技术节点相关的成本和复杂程度的情况下,与设备性能增益的速度快得多。需要新颖的工具和设计方法,不仅可以弥补这些挑战,而且还需要利用新兴技术来实现未来的处理器架构中所需的性能。技术替代品如3D集成吸引了显着兴趣,作为维持密度缩放和性能增长的额外方法。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号