Implications of Gate Misalignment for Ultra-narrow Multi-gate Devices

摘要

Multi-gate devices rely on a very thin body to achieve good electrostatic control. While narrow channel is desirable, narrow source/drain extensions can increase parasitic capacitance. Different layout approaches (tapered source/drain, dog-bone transistor) have been used to alleviate this problem, resulting in quite different currents. Multi-gate devices with L=20nm and W=65nm and excellent device performance were reported. An important aspect of their manufacturability is how important the misalignment of the gate relative to the source and drain is. In this paper we present experimental and simulation data for the 45nm technology node and present interesting results for variable-width transistors.