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The Simulation and Verification of The Passivation layer's Residual Stress Aiming at A Silicon-based fan-out Package Structure

机译:钝化层的残余应力仿真鉴于硅基扇出封装结构的仿真与验证

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In this paper, for a silicon-based fan-out package, through the method of finite element simulation, simulated the distribution of residual stress of the passivation layer after curing process, and analyzed the influence of the change of filling rate and the chip thickness to the passivation layer stress. The simulation results show that the maximum stress distribution on the passivation layer fill gaps and chip surface contact area, the lower filling rate will lead to lower stress; the thinner chip also leads to lower stress. And the fracture failure in contact area of gap and the chip surface in final product verified the simulation results.
机译:本文在硅基扇出包中,通过有限元模拟的方法,模拟固化过程后钝化层的残余应力分布,并分析了灌装速率变化和芯片厚度的影响钝化层应力。仿真结果表明,钝化层填充间隙和芯片表面接触面积的最大应力分布,较低的灌装速率将导致压力降低;较薄的芯片也导致压力降低。并且在最终产品中接触面积的断裂面积和芯片表面验证了模拟结果。

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