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Lead-free and halogen free solder flip chips on board using SMT processes and materials for miniaturization and lower cost

机译:采用SMT工艺和材料的板上无铅和无卤素焊料倒装芯片,可实现微型化和降低成本

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Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them such as with Package on Package (PoP), fine pitch CSP's or solder flipchip on board. This means that the size and pitch of solder balls or pads in the electronic component packages will continue to shrink and that component stacking with so called Package on Package (PoP) and fine-pitch CSP's will continue to be heavily used. Another important factor is that not only is the area density increasing and the drive to make portable electronics thinner also drives thinner components and thereby warpage becomes one of the key challenges. The use of fine pitch CSP and PoP component's, equal and below 0.40mm pitch, poses a number of challenges for PCB Design, SMT Assembly process and Reliability and since the assembly methods and requirements of these are very similar to lead-free solder flipchips this means lead-free solder flipchip on board can be implemented into high volume consumer products at minimal extra cost of process or materials such as flux underfill and last but not least the cost of printed circuit boards. First, a feasible assembly process must be achieved. The assembly process ranges all the way from screen-printing, dipping in flux or paste, reflow soldering in air or nitrogen and underfill. Many factors influence the quality of the assembly process and with the reduced pitch, the process capabilities for both assembly and PCB fabrication will be tested to its limit and beyond. The basic processes to control are screen-printing, pick & place, reflow soldering with the aid of Nitrogen and underfill and by using solder flipchip some of the challenges can actually be eliminated but there will also be some extra challenges such as known good die, wafer feeding and others. Secon- , the correct incoming materials such as PCB material, PCB surface finish, solder paste, dipping flux, underfill and PCB design need to be selected to ensure a high yielding, cost effective and reliable interconnects. Of course, the mechanics of the products makes a big difference as well but it is very product dependent and many of today's products leave little room for designing the mechanics in the most reliable way due to total cost and overall look and size of the products This paper will discuss different design & layout alternatives and assembly & material selection alternatives for using 0.18mm pitch solder flipchips instead of 0.30–0.40mm pitch CSP's and their corresponding challenges. Different flux and underfill materials are evaluated for compatibility with the lead-free solder and halogen free materials and processes. Results from assembly and reliability testing will be presented, in comparison with 0.30mm pitch CSP's on halogen free FR4 substrates with and without underfill.
机译:便携式电子设备的小型化和越来越多的功能集成要求有源和无源组件的封装密度极高。增加包装密度的方法有很多,例如将其堆叠,例如采用PoP封装,细间距CSP或板载焊料倒装芯片。这意味着电子组件封装中的焊球或焊盘的尺寸和间距将继续缩小,并且使用所谓的封装上封装(PoP)和小间距CSP的组件堆叠将继续被广泛使用。另一个重要因素是,不仅面积密度增加,而且使便携式电子产品更薄的驱动力也使组件更薄,因此翘曲成为关键挑战之一。使用等于或小于0.40mm间距的细间距CSP和PoP组件,对PCB设计,SMT组装工艺和可靠性提出了许多挑战,并且由于其组装方法和要求与无铅焊料倒装芯片非常相似,因此意味着板载无铅焊料倒装芯片可以以最小的工艺或材料(例如助焊剂底部填充)成本和额外但最少的印刷电路板成本实施到大批量消费产品中。首先,必须实现可行的组装过程。组装过程包括丝网印刷,浸入助焊剂或焊膏,在空气或氮气中进行回流焊接以及底部填充。许多因素影响组装过程的质量,并且随着间距的减小,组装和PCB制造的过程能力都将受到极限甚至更高的测试。控制的基本过程是丝网印刷,拾取和放置,借助氮气和底部填充进行的回流焊接,以及通过使用倒装芯片进行焊接,实际上可以消除一些挑战,但是还存在一些额外的挑战,例如已知的良好管芯,晶圆喂食和其他。其次,需要选择正确的进料,例如PCB材料,PCB表面光洁度,焊锡膏,浸渍助焊剂,底部填充胶和PCB设计,以确保高产量,高成本效益和可靠的互连。当然,产品的结构原理也有很大的不同,但是它与产品密切相关,并且由于产品的总成本,整体外观和尺寸,当今的许多产品几乎没有以最可靠的方式设计结构的空间。本文将讨论使用0.18mm间距焊料倒装芯片代替0.30–0.40mm间距CSP的不同设计和布局替代方案以及组装和材料选择替代方案及其相应的挑战。评估了不同的助焊剂和底部填充材料与无铅焊料和无卤素材料和工艺的兼容性。将提供组装和可靠性测试的结果,并与带和不带底部填充的无卤素FR4基板上的0.30mm间距CSP进行比较。

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