New challenges emerging on the design of VLSI circuits made of MOSFETs using new gate dielectric materials

摘要

While Quality Electronic Design issues regarding typical MOSFETs constructed by well established techniques and made of SiO/sub 2/ gate dielectrics are yet to optimised, new issues regarding the implementation of MOSFETs having gates made of high-k dielectric materials other than SiO/sub 2/ are being raised during the last years. Parameters such as the high dielectric constant values, extra oxide charges and process related defects have to be taken into account. In this paper, such issues are addressed. The case replacing commonly used parameters of the MOSFET modelling with new ones that will take into account the presence of a material with different properties than that of SiO/sub 2/ is presented and proposals are made. Moreover, a case study is presented, where a memory device is examined. An overall estimation of the proposed procedure is attempted and further work is proposed.