A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

摘要

Up to date, MOSFETs have been made through well established techniques that use SiO_2 as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO_2 as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO_2 is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO_2 devices. A cell layout is provided and the DRAM circuit characteristics are also presented.