For millions of qubits, I/O, wiring, control/readout signal latency, and thermal budget per qubit are challenging. A novel scheme adopting superconducting digital electronics integrated on a System-on-Wafer (SoW) Superconducting Silicon Interconnect Fabric is proposed. We demonstrate the SoW with a fine interconnect pitch <10 μm, (~60 μm) lateral inter-dielet spacing, and a low profile (≤ 1 μm) die-attach. The proposed design can attain a picosecond interconnect latency, a potential nanosecond qubit control latency, and a prospective 10000X reduction in power dissipation. This work is able to fulfill the true potential of quantum computing.
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