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Electrical and Mechanical Performance of Quilt Packaging with Solder Paste by Pin Transfer

机译:通过引脚转移焊膏的被子包装的电气和机械性能

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Electrical and mechanical performance of Quilt Packaging (QP), a 2D system-in-package chip-to-chipinterconnection, is presented. QP employs contacts at the edges of integrated circuit dies along their verticalsurfaces. Based on 3D HFSS simulations, the self-inductance of QP can be less than 0.01 nH, and the selfcapacitancecan be less than 0.034 pF due to the shortness of the interconnection path. QP interconnection usingsolder paste with pin transfer is presented, and mechanical reliability is evaluated. A new pull test systemspecifically designed for QP is presented. The pull force that causes failure in a set of edge interconnects totaling 3mm width of nodules is about 658 gram-force for Sn63Pb37 and 953 gram-force for SAC305.
机译:二维系统级封装芯片对芯片Quilt Packaging(QP)的电气和机械性能 互连,介绍。 QP在集成电路管芯的边缘沿其垂直方向采用触点 表面。基于3D HFSS仿真,QP的自感可以小于0.01 nH,并且自电容 由于互连路径的短路,它可以小于0.034 pF。 QP互连使用 介绍了带有引脚转移的焊膏,并评估了机械可靠性。新的拉力测试系统 介绍了专门为QP设计的。导致一组边缘互连故障的拉力总计3 对于Sn63Pb37,结节的mm宽度约为658克力,对于SAC305为953克力。

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