Integrated wafer thinning process with TSV electroplating for 3D stacking

摘要

This paper presents an optimized integrated thinning process which is dedicated to fabricating ultra thin wafers with through silicon via (TSV). The thinning process is based on blind-vias electroplating, mechanical grinding, wet/dry etching, CMP(chemistry mechanical polishing)and a wafer to wafer handling system developed by previous studies [1,2]. In the study, 60um TSV filled with copper is clearly observed in 40-um-thick 4-inch wafers, and the wafer flatness is successfully controlled to be below 5um. Meanwhile, the integrated thinning process is a low-cost one that only demands direct current (DC) electroplating and a relatively short period of CMP process, which may be applicable to industrial production.