3D Integrated CMOS Device by Using Wafer Stacking and Via-last TSV

摘要

A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybrid wafer bonding brings both seamless copper bonding and void-less underfilling in face-to-face (F2F) and back-to-face (B2F) configurations. The backside-via-last TSV processes provide electrical connection between a TSV and copper/low-k interconnects without causing low-k damage. The low capacitance (around 40 fF) of the TSVs results in the highest level of transmission performance (15 Tbps/W) so far. Additionally, according to ring-oscillator measurements, the keep-out-zone (KOZ) is up to 2 μm from a TSV. This extremely small KOZ is mainly attributed to low residual stress in the silicon surrounding a TSV (i.e., below 50 MPa at 2 μm from a TSV edge).