Suppression of Hole Current in Graphene Transistors with n-type Doped SiC Source/Drain Regions

摘要

To achieve graphene channel transistors which have a high on/off drain current ratio and unipolar behavior of drain current - gate voltage (I_D-V_G) characteristics, we fabricated and characterized top gated graphene channel transistors with n-type doped SiC source/drain regions. The graphene layer was formed on a SiC substrate by high temperature annealing in vacuum, and Al_2O_3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration N_D=4.5×l0~(19)cm~(-3)) and a 4～6 monolayer (ML) graphene channel, ambipolar behavior was observed. On the other hand, when N_D was reduced to 4.5×10~(18)cm~(-3) and a thin graphene layer was used, the suppression of hole current in the I_D-V_G curve was observed.