A Low-Power Dual-Modulus Prescaler in 90nm CMOS Technology

摘要

In PLL design, dual-modulus prescaler is one of the bottlenecks in achieving a higher operation speed. D flip-flop is the key factor limiting the speed of dual-modulus prescaler. By analyzing and improving the structure of Yuan-Svensson TSPC D flip-flop, the dual-modulus prescaler with a high speed, low voltage and low power is designed using TSMC 90nm 1P9M CMOS technology. It can be suitable for WLAN IEEE 802.11a communication standard. The circuit was simulated by Mentor Graphics Eldo. The simulated results show the working frequency is 5.8 GHz with supply voltage 1.2V at room temperature and power dissipation is only 0.8 mW. Its maximum operating frequency reaches 6.25 GHz.