首页> 外文会议>2011 69th Annual Device Research Conference >Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs
【24h】

Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs

机译:金属/锑化物界面上的费米能级钉扎以及基于锑化物的金属S / D肖特基pMOSFET的演示

获取原文

摘要

III–V semiconductors are considered as promising candidates to replace silicon as the channel material in future technology nodes for transistors [1]. III–V n-channel MOSFETs have been extensively studied [2–4], showing high electron mobility. However, one of the most critical challenges in realizing high performance III–V MOSFETs is the difficulties in source/drain (S/D) design including parasitic resistance due to low solubility and poor activation of dopant and the “source starvation” effect due to low density of states [5–6]. Annealing of implant damage after S/D ion-implantation is also more problematic in III–V''s due to the presence of 2 or more atomic species vs. group IV semiconductors (Fig.1). Use of Schottky-barrier (SB) metal S/D is a promising strategy to overcome these limitations [7]. Meanwhile, for III–V based CMOS logic, achieving a high mobility pMOSFET in a III–V channel remains a challenge. Antimony (Sb) based compound semiconductors have the highest electron and hole mobilities amongst all III–V materials. Recently, high performance strained channel InGaSb pMOSFETs [8] have been demonstrated. In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an InxGa1−xSb channel for good hole transport with metal S/D for low access resistance.
机译:在晶体管的未来技术节点中,III-V族半导体被认为是有望替代硅作为沟道材料的有前途的候选材料[1]。 III–V n沟道MOSFET已被广泛研究[2-4],显示出较高的电子迁移率。但是,实现高性能III–V MOSFET的最关键挑战之一是源极/漏极(S / D)设计中的困难,包括由于溶解度低和掺杂剂活化差而引起的寄生电阻,以及由于产生的“源极饥饿”效应低密度状态[5-6]。与IV族半导体相比,S / D离子注入后的注入损伤退火在III-V族中也存在更多问题,这是因为存在两种或更多种原子。肖特基势垒(SB)金属S / D的使用是克服这些局限性的一种有前途的策略[7]。同时,对于基于III–V的CMOS逻辑,在III–V通道中实现高迁移率pMOSFET仍然是一个挑战。在所有III–V材料中,基于锑(Sb)的化合物半导体具有最高的电子和空穴迁移率。最近,已经证明了高性能的应变沟道InGaSb pMOSFET [8]。在本文中,我们研究了金属与锑化物的接触。在p型材料上形成的良好金属接触以及在n型样品上的电流抑制归因于金属/锑化物界面处的费米能级钉扎和价带边缘附近的电荷中性能级。提出并通过实验证明了肖特基势垒S / D p-MOSFET,该晶体管结合了In x Ga 1-x Sb沟道以实现良好的空穴传输,并结合了金属S / D以实现低空穴传输。访问阻力。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号