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Fermi-level pinning at metal/antimonides interface and demonstration of antimonides-based metal S/D Schottky pMOSFETs

机译:金属/锑苷界面的FERMI-LEAL PINNING和锑甙的界面界面和展示的基于抗糖苷的金属S / D肖特基菲特

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III–V semiconductors are considered as promising candidates to replace silicon as the channel material in future technology nodes for transistors [1]. III–V n-channel MOSFETs have been extensively studied [2–4], showing high electron mobility. However, one of the most critical challenges in realizing high performance III–V MOSFETs is the difficulties in source/drain (S/D) design including parasitic resistance due to low solubility and poor activation of dopant and the “source starvation” effect due to low density of states [5–6]. Annealing of implant damage after S/D ion-implantation is also more problematic in III–V's due to the presence of 2 or more atomic species vs. group IV semiconductors (Fig.1). Use of Schottky-barrier (SB) metal S/D is a promising strategy to overcome these limitations [7]. Meanwhile, for III–V based CMOS logic, achieving a high mobility pMOSFET in a III–V channel remains a challenge. Antimony (Sb) based compound semiconductors have the highest electron and hole mobilities amongst all III–V materials. Recently, high performance strained channel InGaSb pMOSFETs [8] have been demonstrated. In this paper, we study the metal contact to antimonides compound. Good metal contact formed on p-type material and current suppression on n-type samples is attributed to the Fermi-level pinning at metal/antimonide interface and charge-neutral level being near the valence band edge. Schottky-barrier S/D p-MOSFETs is proposed and experimentally demonstrated which combines an InxGa1−xSb channel for good hole transport with metal S/D for low access resistance.
机译:III-V半导体被认为是希望将硅替换为晶体管的未来技术节点中的硅膜的候选者[1]。 III-V N沟道MOSFET已被广泛研究[2-4],显示出高电子迁移率。然而,实现高性能III-V MOSFET的最关键挑战之一是源/漏极(S / D)设计中的困难,包括由于低溶解度和掺杂剂的激活差和掺杂剂的差和“来源饥饿”效应而导致的寄生电阻状态低密度[5-6]。 S / D离子植入后的植入物损伤的退火在III-V之后也是更成物的,因为存在2个或更多种原子种与第IV组半导体(图1)。使用肖特基屏障(SB)金属S / D是一种克服这些限制的有希望的策略[7]。同时,对于基于III-V基于的CMOS逻辑,在III-V频道中实现高迁移率PMOSFET仍然是一个挑战。锑(Sb)基复合半导体具有所有III-V材料中的最高电子和孔迁移率。最近,已经证明了高性能应变通道IngaSB PMOSFET [8]。在本文中,我们研究金属接触至锑化合物。在p型材料上形成的良好金属触点和N型样品的电流抑制归因于金属/抗衍生物界面处的FERMI级钉扎在价带边缘附近的电荷中性水平。提出和实验证明的肖特基 - 屏障S / D P-MOSFET在 X / INF> GA 1-X / INF> SB通道中,用于金属S / D的良好空穴传输进入电阻。

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