ESD robust DeMOS devices in advanced CMOS technologies

摘要

Improvement of ∼5X in the IT2 (3.3mA/μm) of a grounded gate N-DeMOS device compared to a standard design is achieved by simple layout variations with a minor impact on its footprint. Robustness of P-DeMOS devices is shown to be further increased by additional p implant in drain region. Electrical and thermal instabilities are studied by Transmission Line Pulsing (TLP), Transient Interferometric Mapping (TIM) method and 3D TCAD simulations.