As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC, at the IC package, at the module, at the hybrid, the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability, although the development of fine-pitch substrates and assembly technology has narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process. This paper provides a comparison of different commonly used technologies including flip-chip, chip-size and wafer level package methodologies detailed in a new publication, IPC-7094. The IPC document describes the design and assembly challenges for implementing flip-chip technology in a direct chip attach (DCA) assembly. It considers the effect of bare die or die-size components in an uncased or minimally cased format, the impact on current component characteristics and reviews the appropriate assembly methodology. The focus of the IPC document is to provide useful and practical information to those who are mounting bare die or die size components or those who are considering flip -chip process implementation.
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