Efficient mask data preparation for the variable shaped e-beam writing system focusing on memory devices

摘要

To cope with the sub-100nm technology in the mask making industry, a variable-shaped e-beam (VSB) writing system is one of the solutions due to its high pattern fidelity. The VSB writing system, however, requires different mask data preparation comparing to the traditional raster scan writing system. Especially, in memory devices, mask manufacturers are confronted with difficult problems such as unpredictably growing mask turn-around-time (TAT). Mainly explosively increasing data volume by aggressive resolution enhancement techniques (RET) causes the data conversion time protracted. On account of the VSB system's e-beam exposure characteristics, its writing time is affected by the result of data conversion. The data conversion aimed at reducing the writing time takes a few days, especially in case of critical layers of memory devices which are aggressively deployed with RET such as optical proximity correction (OPC), and sub-resolution assist feature (SRAF). To shorten the mask TAT, the data conversion process should consider the requirements of the VSB writing system at the same time. In addition, as the design rule has been shrunk, the tighter critical dimension (CD) control is required in the data conversion process. Our objectives to shorten the mask TAT of the VSB system are to reduce the writing time, to reduce the data conversion time and to improve the CD control. The flat data operation produces the better result in the writing time but the data conversion time increases exponentially as the design density of memory devices is increased. The data conversion of the hierarchical data operation is faster but the writing time is longer than that of the flat data operation. To reduce the data conversion time while retaining the optimal writing time, we propose the mixed-mode data processing method, in which the hierarchical data operation is applied on memory cells and the flat data operation is applied on peripheral circuits. For each area, different fracturing strategies are applied, too. The polygon-aware fracturing method is applied to improve the CD control within memory cells, and the selective one-directional fracturing method is applied to reduce the writing time within peripheral circuits.