PLANARIZATION ISSUES FOR THREE-DIMENSIONAL (3D) ICs AND WAFER-SCALE PACKAGING (WSP) APPLICATIONS

摘要

Monolithic wafer-scale three-dimensional (3D) ICs based upon bonding of processed wafers and wafer-scale packaging based upon attachment of a processed wafer to a first-level packaging substrate require additional planarization considerations compared to conventional planar ICs and packaging of chips. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-scale 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric glues, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect using copper damascene patterning. The contribution of bonding glue to relaxing pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.