Distributed memory architecture for parallel processing has the advantages of high levels of flexibility and scala-bility. However due to the higher communication startup cost in these machines frequent communication is very ex-pensive. Tiling is a technique for extraction of parallelism which groups the iterations into blocks called tiles such that sequential traversal of the tiles covers the entire iteration space. Size of the tile is very important in determining the efficiency of execution. Larger the tile size lesser is the com-munication cost and vice versa. In this paper a method for determining the optimal tile size for tiling of two dimen-sional iteration spaces of a DOACROSS loop nest is pre-sented. The results reported in this work are based on a wavefront execution of the tiles.
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