Electrical Performance of a Lead Frame Csp and A Wafer Level CSo for Dram Applications

摘要

CSP (Chip Size Package) is expected to be widely used in D-RDRAM (Direct Rambus DRAM) for its higher electrical performance as well as in PDA (Personal Digital Assistant) applications for its smaller size and lighter weight. In this study, the electrical performance of a LF-CSP (Lead Frame type CSP) and a WL-CSP (Wafer Level type CSP) having a high potential to be used in DRAM applications are compared with that of the current TSOP. In order to do this, the RLC parameters of the packages are extracted and the noise level and delay time with these three packages are computed by SI (Signal Integrity) simulation and compared with each other. Also, the three packages are assembled and their DC/AC characteristics are measured and compared with the simulation result in order to verify the validity of the simulation result. The result shows that there is a good agreement between the simulation and measurement and the CSPs have better electrical performance than TSOP.