Chemical Mechanical Polishing for Planarisation of Advanced IC Processes

摘要

An CMP process will be presented which is optimised for low layout sensitivity and good uniformity. The best results were obtained by using a stack of two polishing cloths, instead of a single cloth. This results in a better planarisation capability while improving the uniformity compared to a single hard polishing cloth. The feasibility of the novel CMP process was demonstrated on a 64k SRAM.