PAVING THE WAY TO 3D: FROM PASSIVE TO ACTIVE INTERPOSERS

摘要

Passive interposers have focused a lot of attention these last years for advanced packaging, especially in the field of FPGA. While the demand will be in the coming years more and more pronounced for high performance computing (HPC), passive interposers are already facing their own limits in terms of size (>25×25 mm~2) and integration (wrapage, interconnects pitch, thickness...) and performance (signal integrity). In this paper, we report what are the current technological developments regarding Through-Silicon-Vias (TSV), chip interconnects temporary bonding techniques and stress management and what would be their impact on the next generation of interposers. In a second step, we discuss the perspectives, advantages and challenges of moving towards active interposers (i.e. with embedded transistors) and their impact on HPC architecture roadmap.