COPPER ELECTROPLATING FOR HIGH DENSITY 3D THROUGH SILICON VIA INTERCONNECTS

摘要

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times better than today's advanced MCMs. It overcomes the RC delays of long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and by providing a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, although TSVs have great potential, there are many fabrication issues that must be considered. This paper will discuss those issues in detail and explain the fabrication process under development at the University of Arkansas' High Density Electronics Center (HiDEC). There are five main areas in the fabrication of TSVs that mill be discussed: formation of the vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and system integration. The goal of this project is to create high aspect ratio vias that are two to five microns in diameter on 20-micron pitch in wafers that are subsequently thinned to 10 to 15 microns thick.