Voltage limiters suitable to DRAMs with substrate-plate electrode memory cells

摘要

Substrate-plate electrode (SPE) memory cells, like BSE cell [1], SPT cell [2], and TTC [3], are foreseen as candidate cells for DRAMs of 4-Mbits or beyond, because of their compact cell size and inherent immunity against alpha-particle induced soft errors, SPE cells consist of the buried storage electrode in a capacitor trench and the heavily doped substrate as the capacitor counter-electrode. Therefore, SPE cells don't need the extra cell-plate electrode wiring, which is needed for the conventional trench cells. Figure 1 shows a diagram for a typical SPE cell, a BSE cell. To obtain sufficient operational margin for DRAMs with SPE cells, as the cell storage voltage varies approximately in proportion to the substrate voltage (Vsub) variation, Vsub variations should be suppressed.