Dynamic random-access memory (DRAM) with stage for restoring memory cells, comprising three double-gate p-MOS transistors connected between higher supply voltage and pair of bit lines

摘要

The memory store comprises a memory array (MA) of cells (2) laid out in rows and columns, where for each column there is a sense amplifier (SA) used in write operation for polarizing a selection of cells to either a supply voltage (Vdd) or to a lower voltage, and in read operation for determining if the level of stored charge is higher or lower than a predetermined level, an isolation stage (3) for separating the memory array from the read/write circuit, and a restoring stage (19) for increasing the charge stored in memory cell beyond the two pre-determined levels. The restoring stage (19) comprises a double-gate p-MOS transistor (P24) connected between a higher supply voltage (VRS) terminal and a node of interconnection of two double-gate p-MOS transistors (P22,P23) whose sources are cross-connected to the gates and constitute the input/output terminals (OUT20,OUT21). The isolation stage (3) comprises two double-gate n-MOS transistors (N10,N11). The precharge stage (16) comprises two double-gate n-MOS transistors (N17,N18). The precharging ad balancing stage (12) for the sense amplifier (SA) comprises three p-MOS transistors (P13,P14,P15) with common gate, where the midpoint of the pair (P13,P14) is connected to the supply voltage (Vdd) terminal and the third transistor (P15) short-circuits the sense amplifier terminals (SA1,SA2). The method for writing data in memory cells includes the polarization of the isolation stage (3) so that it is partially open and the validation of the restoring stage (19). The method for restoring data in memory cell includes the polarization of the isolation stage (3) so that it is completely open, and the validation of the restoring stage (19). The method for controlling the memory cell includes the provision of a control signal (BLPASS) having three levels, where the first level activates the complete opening of the isolation stage, the second level completely inhibits the isolation stage, and the third level activates or inhibits each double-gate n-MOS transistor (N10,N11) according to the state of the sense amplifier input/output terminal (SA1,SA2).