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Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

机译:采用相控全硅化(PC-FUSI)技术的45nm节点LSTP和LOP器件的双功函数Ni-Silicide / HfSiON栅堆叠

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We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.
机译:我们提出了一种适用于45nm节点LOP和LSTP CMOS的全硅化(FUSI)金属/高k栅堆叠的新阈值电压(Vth)控制技术。关键是通过在硅化退火之前改变Ni膜的厚度来控制FUSI硅化镍的相控。结果,形成了Ni / sub 3 / Si和NiSi / sub 2 /,其在HfSiON上的有效功函数(WFs)分别为4.8eV和4.4eV,通过/ spl plusmn /大大偏离了Si-midgap。 0.2eV。同时,已知在SiO / sub 2 /上的NiSi的Vth控制中成功的掺杂剂偏析方法不适用于HfSiON。利用Ni / sub 3 / Si-PMOS和NiSi / sub 2 / -NMOS晶体管,可以满足LSTP和LOP要求,实现了广泛的Vth调谐。同时,在约2.0 nm的电厚度(Tinv)时,泄漏抑制性能优于45nm节点目标。此外,我们的相控全硅化(PC-FUSI)器件还具有出色的迁移率特性。

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