A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop

摘要

A fully-differential 2-GHz phase-locked loop (PLL) was designed and fabricated in 0.18-mum CMOS process. The PLL rejects the common noise due to fully-differential VCO and differential charge pump. The VCO has a 16.15% tuning range (from 1.8998GHz to 2.2335GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). With the pn-junction varactors, the phase noise of the VCO varies only about 2dB in the tuning range. The current consumption of the PLL is only about 6.1mA from a 1.8 V power supply. It is comparable to the results reported in recent literatures. The phase noise of the PLL at 2.033 GHz can achieve -117.17dBc/Hz at 1 MHz frequency offset from the carrier.