A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 驴m CMOS

摘要

A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (>250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Spectre simulation in a digital 0.13mum CMOS process. The chip occupies an active area of 0.54mm²