A 10-bit 500-MHz 55-mW CMOS ADC.

摘要

Analog-to-digital converters (ADCs) are widely used in electronics systems with applications in communication systems, bio-medical systems and instrumentation. With continuous advancement in the CMOS technology many of the digital signal processing (DSP) based approaches to assist the inherent analog processing have now become viable, resulting in new architectures achieving either a low power dissipation or a high conversion rate or both.;This research proposes a pipelined ADC calibration technique that allows the use of high-speed, low-power, and yet inaccurate op amps. Designed in 90-nm CMOS technology, a 10-bit prototype digitizes a 233-MHz input with an SNDR of 53 dB, the highest combination reported in the literature for a power consumption of 55 mW. The prototype consists of 14 stages and calibrates capacitor mismatches and nonlinearity and gain error of op amps by means of a resistor-ladder DAC having 11-bit linearity. Employing a two-stage op amp with a bandwidth of 10 GHz and a gain of 25, the ADC achieves a DNL of 0.4 LSB, and INL of 1 LSB.