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Ultra thin (>3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing

机译:通过原位快速热处理制造的超薄(> 3 nm)高质量氮化物/氧化物堆叠栅极电介质

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In this paper, ultra thin (>3 nm) Si/sub 3/N/sub 4//SiO/sub 2/ stack layer with significant lower leakage current, superior boron diffusion barrier properties, and reliability compared with SiO/sub 2/ of identical thickness have been fabricated by in-situ RTP processing. These results demonstrate for the first time that ultra thin LPCVD Si/sub 3/N/sub 4/ can be used as gate dielectrics, contrary to those conclusions made previously on thicker LPCVD Si/sub 3/N/sub 4/.
机译:本文中的超薄(> 3 nm)Si / sub 3 / N / sub 4 // SiO / sub 2 /堆叠层具有比SiO / sub 2 /更低的漏电流,优异的硼扩散阻挡性能和可靠性通过原位RTP处理已经制造出厚度相同的材料。这些结果首次证明,超薄LPCVD Si / sub 3 / N / sub 4 /可用作栅极电介质,这与先前在较厚LPCVD Si / sub 3 / N / sub 4 /上得出的结论相反。

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