A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop

摘要

A dual-modulus divide-by-128/129 prescaler has been designed using 0.6-/spl mu/m CMOS technology. A new charge sharing free dynamic D-flip-flop for high-speed operation and low-power consumption is examined in the circuits. The simulated maximum operating frequency and the current consumption of the prescaler are 1.97-GHz and 7.453 mA at 5-V supply voltage, respectively.