Field programmable gate array is mainly composed of the interconnection resources area. Related defects/faults are therefore more probable than defects/faults in other regions of the chip. In this paper we propose a new approach tolerating defects/faults in interconnection resources. This approach is based on the modification of the switching block structure so that defects/faults could be avoided. Defects/faults are avoided with only an average of 3% delay overhead and partial modification of the original data. The yield is significantly improved comparing with actual chips. The area overhead is required in this approach. However, it is proved that it is reasonable comparing with other approaches.
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