Low latency EDRAM main memory subsystem for 66 MHz bus operation

摘要

A 16-64 MByte two-way interleaved enhanced DRAM main memory subsystem for 66 MHz 64-bit microprocessors (such as Pentium, PowerPC, R4400, and Alpha) is described. The subsystem integrates 16-64 MBytes of 35 ns random access fast DRAM, a two-way interleaved 8-32 kByte 15 ns SRAM cache, and a 8-32 kByte wide DRAM to SRAM bus structure in a board footprint of only six square inches. In addition to achieving a burst read/write bandwidth of 528 MByte/s at 66 MHz, this subsystem achieves a fast 15 ns initial latency on read hit and 35 ns on read miss accesses. This same memory configuration should be able to support the 80 MHz bus rates required by the highest speed members of these processor families.