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Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications
Integration of high density cross-point memory and CMOS logic for high density low latency eNVM and eDRAM applications
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机译:高密度低延迟ENVM和EDRAM应用的高密度交叉点存储器和CMOS逻辑的集成
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摘要
An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.
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