Halo Implantation Optimization for 65nm Low Power PMOS Device Inverse Narrow Width Effect Improvement

摘要

Device with shallow trench isolation (STI) has inverse narrow width effect (INWE), that is the threshold voltage of narrow width transistors is lower than that of large width transistors. The conventional methods of improving INWE focus on STI module optimization, such as active area corner rounding, step height and divot control. In this paper, a new approach by implant optimization is proposed to improve INWE. For low power PMOS device, phosphorus halo implant is often used for its lower diode leakage characteristics. This paper reports optimized dual halo implant approach with both arsenic and phosphorus implants to improve INWE. This approach gives larger Gm*Rout and lower digital product chip stand-by current without reliability degradation.