New Methods to Efficiently Test the Reliability of Plated Vias and to Model Plated Via Life from Laminate Material Data

摘要

This paper continues work by Sun Microsystems and the University of Maryland, CALCE to predict plated through via life using laminate material properties, plated copper material properties, and the physical via geometry to model via life. The new method presented in this paper uses non-linear laminate material properties and a damage-fatigue model to predict the accumulated damage to a plated through via as it is thermally cycled through assembly and field life conditions. Copper is a ductile metal so it is possible to construct a Log-Stress versus Log-Life plot that follows an Inverse Power Law (IPL). The key to doing a Log-Stress versus Log-Life plot is developing the relationship of stress versus temperature of the laminate material. Use of a Log-Stress versus Log-Life plot allows increased testing efficiency since you can perform an accurate life analysis by testing at only the high and low temperature extremes. Once the Log-S versus Log-N plot is constructed, it is possible to predict plated through via life over a wide range of temperatures. For this paper, we will use thermal cycle to failure test data obtained from Interconnect Stress Test (IST), but the analytical methods developed apply equally to other thermal cycle methods like Highly Accelerated Thermal Shock (HATS) and Air-to-Air Thermal Shock (AATS). Last, a Finite Element Model simulation is conducted that uses material properties that are easy to obtain and is then validated against the large database from IST testing at multiple temperatures. Once the Finite Element Model validation is complete, the model is used to make assembly and field life predictions for two case studies involving thick, complex printed wiring boards.