Semiconductor Process Line Scheduling Expert System

摘要

To ensure short turn-around time under the condition of increasing demand on broader product mix, scheduling of the semiconductor process line must be optimized. This is particularly a problem for prototyping lines which deal with a variety of products such as, DRAM, SRAM, Bipolar, and CMOS, etc. However, since semiconductor fabrication is characterized by a multi-stage process with reentrant flows and a large number of process steps[1], obtaining optimized scheduling within a reasonably short period is very difficult.