How to Avoid the Pitfalls Of Paralleling MOSFETs

摘要

In order to produce designs that satisfy the current demands of the Personal Computer (PC) industry, engineers have resorted in many cases to paralleling MOSFETs to reduce the losses and increase the power converters efficiency (ζ). Traditionally, this has been an easy decision to make since the switching frequency and the switching speeds were kept low and the current sharing between the paralleled MOSFETs depended mainly upon the Pulse Width Modulation (PWM) ICs and MOSFETs, we believe that this decision must be taken with greater care to achieve the same desirable results we came to expect and achieve. In this paper we will show that there are several conditions that must be met to achieve a successful, reliable and robust design. We will also show some of the pitfalls that may lead to unbalanced current sharing and unbalanced sharing of dynamic losses causing excessive power dissipation and poor reliability or even worse, leading to failure of the device with the most stresses. The analysis will be carried out using Worst Case conditions and also some Extreme Value Analysis will be conducted to allow us to understand the potential rare problems that may be encountered when a company manufactures several million PCs during the life span of a given design. Several million PC is rather a common occurrence of a successful design and must be taken into account during the design phase.