A DFT and Test Pattern Generation Methodology for an ARM Powered~(~R) SoC Design

摘要

This paper describes the Design-for-testability (DFT) Methodology for an ARM powered~(~R) SoC (System-on-a-chip) design which is named by Garfield and used for hand-held computing. Various test methods, including scan insertion. Memory BIST (Built-in Self-test), boundary scan and functional test, and the strategies merging the above methods in SoC design will be discussed in detail.